The present invention is directed to improvements to an instruction pipeline in a microprocessor. In particular, the present invention is directed to a system and method for event and micro-branch misprediction recovery in an instruction pipeline.
Modern microprocessors include instruction pipelines in order to increase program execution speeds. Instruction pipelines typically include a number of units, each unit operating in cooperation with other units in the pipeline. One exemplary pipeline, found in, for example, Intel""s Pentium(copyright) Pro microprocessor, includes an instruction fetch unit (IFU), an instruction decode unit (ID), a micro-code sequencer (MS), an allocation unit (ALLOC), an instruction execution unit (EX) and a write back unit (WB). The instruction fetch unit fetches program instructions. The instruction decode unit decodes macro-code instructions into a set number of micro-ops. However, if the macro-code instruction decodes into an a number of micro-ops that is greater than the set number, control is passed to the micro-code sequencer. The micro-code sequencer then provides the remaining micro-ops. The micro-code sequencer is also responsible for providing instructions to the execution unit when the processor must execute micro-code, for example, during event recovery. The allocation unit assigns a sequence number to each micro-op and stores each micro-op in an instruction pool. The execution unit executes the micro-ops. Finally, the write back unit retires instructions.
The instruction pipeline of Intel""s Pentium(copyright) Pro microprocessor also includes branch prediction circuitry. In particular, when the instruction fetch unit fetches a branch instruction, branch prediction circuitry determines which instruction should be fetched next, i.e., the next linear instruction or the instruction at the branch target address.
During operation, the execution unit executes the micro-ops in the instruction pool in any order possible as data and execution units required for each micro-op becomes available. If the execution unit detects a branch instruction misprediction, the microprocessor must have a fast way to recover, i.e., to begin processing the proper instruction.
Accordingly, for each micro-op it processes, the allocation unit stores in a branch information table (BIT) a pointer to the next linear macro-code instruction (NLIP). Then, when the execution unit detects a branch misprediction, the execution unit signals the BIT to provide the appropriate instruction address with which to restart the instruction pipeline, e.g., the instruction pointed to by the NLIP or another address. Since information is stored in the BIT for each micro-op, the process of storing the information should be as efficient as possible. There is a need to further improve the efficiency of storing this information in the BIT.
In the Intel Pentium(copyright) Pro microprocessor, if the micro-code sequencer determines that the instruction pipeline should be restarted at the current instruction, the address of the current instruction must be calculated, i.e., the address of the current instruction is NLIP minus the length of the current instruction. Since macro-code instructions are not a uniform length, the instruction length of each instruction is passed in a data path, along with the instruction itself. Moreover, in the Intel Pentium(copyright) Pro microprocessor, other information needed by the micro-code sequencer, such as, for example, an indication as to whether a particular micro-op originated from the micro-code sequencer or another pipeline unit, is also transmitted in a dedicated data path. Data paths in microprocessors use expensive resources. Accordingly, there is a need to reduce the number of data paths associated with instruction pipeline restarts, particularly with respect to restarts associated with machine state recovery.
In accordance with an exemplary embodiment of the present invention, a pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch instruction misprediction. The pipelined microprocessor further includes a decode stage which stores recovery state information for respective instructions and responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event.